1. Field of the Invention
The present invention relates to an electronic circuit for performing clock gating on a clock signal supplied to a clock system in which both edges of the signal are used.
2. Background Art
Conventionally, in some cases, flip-flops and memories for capturing data on both edges of clocks are used in semiconductor integrated circuits. Such flip-flops and memories for capturing data on both edges of clocks can achieve not only higher clock speeds but also a reduction in the charge and discharge of clock systems by half. Thus such flip-flops and memories have been used for low-power LSIs.
One of basic power-saving techniques is clock gating. Clock gating is a technique for temporarily stopping the transmission of clocks to circuits when the circuit sections do not need to operate in semiconductor integrated circuits. The clock gating technique can reduce excessive current consumption.
For example, in a period during which the supply of an output clock signal is stopped, a conventional electronic circuit (a gate circuit for clocks) for performing clock gating latches a state of the output clock signal when the supply of the output clock signal is stopped, and outputs the signal to a flip-flop circuit. When the supply of the output clock signal is resumed, the output clock signal is outputted to the flip-flop circuit in phase or in opposite phase with an input clock signal such that the state of the output clock signal when the supply of the output clock signal is stopped agrees with the state of the input clock signal when the supply of the output clock signal is resumed. Thus it is possible to prevent the occurrence of an excessive edge on the output clock signal (see Japanese Patent Laid-Open Publication No. 11-274905).
By using flip-flops and memories in which data is captured on both of the rising edge and the falling edge of a clock as described in the related art, the clock frequency (operating frequency) can be increased as compared with ordinary flip-flops and memories in which data is captured only on the rising edge (or the falling edge). Therefore, such flip-flops and memories have been used for high-speed LSIs.
Furthermore, since the charge and discharge of a clock system can be reduced by half using both edges of a clock, such a technique is also used for low-power LSIs.
However, the electronic circuit of the related art requires at least two exclusive-OR circuits and two latch circuits, resulting in a complicated circuit configuration and an increase in circuit area.